1. Field of the Invention
The present invention relates to a diode circuit and rectifier and, more particularly, to a MOS transistor circuit manufactured by the CMOS process for simulating a zero cut-in voltage diode and a zero cut-in voltage rectifier including the diode.
2. Description of Related Art
The conventional AC to DC full wave rectifier is generally formed by diodes. Since the diode has a cut-in voltage of 0.6V, the rectifier will have a power loss in voltage conversion. Particularly, when the input voltage is small, the negative influence caused by such a power loss becomes obvious and unacceptable.
In the field of contactless ICs and the like, the power supply of the IC is a low power AC power supply in which the power is generated by the induction of a coil, and thus, the efficiency by which the power supply output is rectified will directly affect the use range of the IC. As a result, the operating efficiency of such an IC is determined by the performance of the rectifier.
In the aforementioned AC to DC full wave rectifier, a popular circuit known as a full wave bridge rectifier, illustrated in FIG. 6, has four diodes 902 to 905 connected in a bridge structure. With such a circuit, when the AC power source 901 applies an AC signal to the full wave rectifier, the diodes 902 and 905 are turned on if the applied waveform ACIN1 greater than ACIN2. The AC signal then charges the capacitor 906 through the diodes 902 and 905. However, if ACIN2 greater than ACIN1, the diodes 903 and 904 are turned on, and the AC signal charges the capacitor 906 through the diodes 903 and 904. As such, the AC power can be rectified to produce a DC power.
FIG. 7 is the rectifying waveform of a bridge rectifier, which shows that, due to the influence of the cut-in voltage of the diode, the rectified DC voltage VDD only has a maximum value of Vacxe2x88x922*Vd, where Vac is the voltage peak value of the AC power source 901 and Vd is the cut-in voltage of the diode. Therefore, the rectifying performance of the rectifier is greatly degraded.
In order to solve such a problem, FIG. 8 shows another conventional rectifier circuit, which uses metal oxide semiconductor (MOS) transistors 914 and 915 with N-type substrate to control the diodes for performing the rectifying operation of AC to DC conversion. When ACIN1xe2x88x92ACIN2 greater than Vtn (Vtn is the threshold voltage of N-type MOS transistor), the N-type MOS transistor 915 is turned on, and the ACIN2 is applied to a lowest voltage VSS. When ACIN1xe2x88x92VDD greater than Vd, the diode 912 is turned on, and the AC power source starts to charge VDD. When ACIN2xe2x88x92ACIN1 greater than Vtn, the N-type MOS transistor 914 is turned on, ACIN1 is applied to a lowest voltage VSS. When ACIN2xe2x88x92VDD greater than Vd, the diode 913 is turned on, and the AC voltage source starts to charge the VDD.
FIG. 9 is a rectifying waveform of the rectifier circuit shown in FIG. 8. In comparison with the waveform shown in FIG. 7, it is known that this improved rectifier circuit is able to reduce a voltage drop equal to one cut-in voltage of a diode. That is, the maximum value of the DC voltage VDD is only improved to be Vacxe2x88x92Vd. Under a condition of no current load, there is still a voltage loss of 0.6V. Thus, the influence of the cut-in voltage can not be completely removed.
In order to entirely remove the cut-in voltage of the diode so that the maximum value of the VDD is Vac, U.S. Pat. No. 5,825,214 granted to Klosa discloses an xe2x80x9cIntegrated circuit arrangement with diode characteristicxe2x80x9d for replacing the conventional diodes to realize a rectifier with zero cut-in voltage. The schematic view of the circuit is illustrated in FIG. 10, which comprises three inverters 921, 922, and 923 and a P-type MOS transistor 924 for being used as a switch. The input end and output end of the inverter 921 are connected together, and thus the output voltage level is automatically set at the trigger point of the inverter. This voltage will change positively with the level of the supplying power. The voltage level set by the inverter 921 is directly applied to the input end of the inverter 922 which receives power from an AC input ACIN. The two inverters 921 and 922 have the same size and characteristic. Therefore, when the ACIN is smaller than the VDD, the input of the inverter 922 is considered to be a high voltage level. Through the inverter 923, the P-type MOS transistor 924 is turned off so as to avoid a leakage current. On the other hand, when the ACIN is larger than the VDD, the input of the inverter 922 is considered to be a low voltage level, the P-type MOS transistor 924 is turned on through the inverter 923, so as to charge VDD.
In the aforementioned circuit, the P-type MOS transistor 924 can be turned on completely to provide the advantage of zero cut-in voltage. However, if the inverters 921 and 922 are operating at a high speed, it is inevitable that a high current loss problem will be encountered. Therefore, the overall efficiency of the rectifier is unsatisfactory due to such a current loss. Consequently, it is desirable to provide an improved circuit to mitigate and/or obviate the aforementioned problems.
Accordingly, the object of the present invention is to provide a circuit for simulating a zero cut-in voltage diode and a rectifier having a zero cut-in voltage characteristic, so as to improve the efficiency of rectifying, reduce the current loss, and avoid the output voltage drop caused by the cut-in voltage of the diode.
In accordance with a first aspect of the present invention, there is provided a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising: a constant bias circuit having a resistor and a N-type MOS transistor, the N-type MOS transistor having a drain connected to the resistor and a gate connected to the drain; a first N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second N-type MOS transistor having a gate connected to the gate of the N-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first P-type MOS transistor and a second P-type MOS transistor connected in a cross couple structure which are coupled to the first and second N-type MOS transistors, whereby a high voltage level of the AC voltage input is applied to a high voltage level of the DC voltage output, and a low voltage level of the AC voltage input charges a low voltage level of the DC voltage output through one of the zero cut-in voltage diodes.
In accordance with a second aspect of the present invention, there is provided a circuit for simulating zero cut-in voltage diode comprising: a first N-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first N-type MOS transistor for forming a bias circuit; and a second N-type MOS transistor with the same characteristic as the first N-type MOS transistor, having a gate connected to the gate of the first N-type MOS transistor; wherein the first N-type MOS transistor is controlled by the resistor to be biased almost to a threshold voltage.
In accordance with a third aspect of the present invention, there is provided a rectifier having zero cut-in voltage characteristic for converting AC voltage input to DC voltage output, comprising: a constant bias circuit having a resistor and a P-type MOS transistor, the P-type MOS transistor having a drain connected to the resistor, and a gate connected to the drain; a first P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form a zero cut-in voltage diode; a second P-type MOS transistor having a gate connected to the gate of the P-type MOS transistor of the bias circuit, so as to form another zero cut-in voltage diode; and a first N-type MOS transistor and a second N-type MOS transistor connected in a cross couple structure which are coupled to the first and second P-type MOS transistors, whereby a low voltage level of the AC voltage input is applied to a low voltage level of the DC voltage output, and a high voltage level of the AC voltage input charges a high voltage level of the DC voltage output through one of the zero cut-in voltage diodes.
In accordance with a fourth aspect of the present invention, there is provided a circuit for simulating zero cut-in voltage diode comprising: a first P-type MOS transistor having a gate and a drain connected together; a resistor connected to the drain of the first P-type MOS transistor, so as to form a bias circuit; and a second P-type MOS transistor with the same characteristic as the first P-type MOS transistor, having a gate connected to the gate of the first P-type MOS transistor; wherein the first P-type MOS transistor is controlled by the resistor to be based to VDDxe2x88x92Vtp, where VDD represents a high voltage level of a DC voltage input and Vtp is a threshold voltage of the P-type MOS transistor.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.